1. Field of the Invention
The present invention pertains to the field of computer graphic systems. More particularly, this invention relates to an interface controller for frame buffer memory devices that provide a write mostly architecture for accelerated graphics rendering operations.
2. Background
Prior computer graphics systems typically employ a frame buffer comprised of video random access memory (VRAM) chips. The VRAM chips store a set of pixel data that defines an image for display on display device. Typically, a rendering controller in such a system renders the image and writes the pixel data into the VRAM chips. In such a system, a random access memory digital to analog conversion device (RAMDAC) typically accesses the pixel data from the VRAM chips and performs color lookup table and digital to analog conversion functions on the pixel data.
Prior VRAM chips typically contain a dynamic random access memory (DRAM) array along with a random access port and a serial access port. Typically, the RAMDAC accesses the DRAM array of a VRAM chip through the serial access port, and the rendering controller accesses the DRAM array through the random access port according to DRAM page mode access. Unfortunately, the DRAM page mode mechanism of such prior VRAM chips delivers severely reduced pixel access speeds if the rendering controller traverses more than two or three rows of the raster scan while drawing a line. Moreover, read-modify-write operations commonly employed during rendering operations are significantly slower than write operations to such prior VRAM chips.
A computer graphic system may employ a frame buffer comprised of frame buffer random access memory (FBRAM) chips. Such FBRAM chips include a DRAM core area that store a set of pixel data that defines an image for display on a display device. Typically, a rendering controller in such a graphic system renders the image and writes the corresponding pixel data into the FBRAM chips.
Such FBRAM chips provide increased throughput to the DRAM cores by providing two levels of two-dimensional area caches. For example, such FBRAM chips provide a level one (L1) pixel cache that reflects preselected areas of the DRAM core. Such FBRAM chips also provide a level two (L2) cache closely coupled to the DRAM core of the FBRAM chip. Such FBRAM chips provide improved rendering throughput by converting the typical read-modify-write frame buffer access cycle into a write mostly transaction at the input pins of the FBRAM devices.
However, the rendering throughput to such a frame buffer having FBRAM chips is reduced for pixel accesses that result in cache misses to either the L1 or the L2 caches or both. A pixel access in such a system targeted for an area of the DRAM core that is not resident in the L1 or the L2 caches requires that the pixel operation be stalled while the missing cache block is fetched from the DRAM core. Such operations in the FBRAM chips for fetching missed cache blocks stalls the rendering pipeline inputs into the FBRAM chips and slows overall rendering speed.